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3SK323
Si Nch Dual Gate MOS FET UHF RF LOW NOISE Amplifier
REJ03G0531-0100 Rev.1.00 May 18.2005
Features
* * * * Low noise characteristics; NF = 1.0 dB typ. (at f = 900 MHz) High gain characteristics; PG = 24 dB typ. (at f = 900 MHz) Capable low voltage operation; +B = 3.5 V High Endurance Voltage; VDS = 6 V
Outline
RENESAS Package code: PLSP0004ZA-A (Package name: MPAK-4)
2 3 1 4
1. Source 2. Gate1 3. Gate2 4. Drain
Notes:
1. Marking is "UG-".
Absolute Maximum Ratings
(Ta = 25C)
Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Symbol VDS VG1S VG2S Ratings 6 +6 -6 +6 -6 20 300 150 -55 to +150 Unit V V V mA mW C C
Drain current ID Channel power dissipation Pch*2 Channel temperature Tch Storage temperature Tstg Notes: 2. Value on the glass epoxy board (50 mm x 40 mm x 1 mm).
Rev.1.00, May 18,2005, page 1 of 7
3SK323
Electrical Characteristics
(Ta = 25C)
Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current Gate1 to source cutoff voltage Gate2 to source cutoff voltage Forward transfer admittance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) |yfs| PG NF Min 6 6 6 -- -- 0 0.3 30 20 -- Typ -- -- -- -- -- 0.5 0.7 42 24 1.0 Max -- -- -- 100 100 1 1.1 -- -- 1.6 Unit V V V nA nA V V mS dB dB Test Conditions ID = 200 A, VG1S = VG2S = 0 IG1 = 10 A, VG2S = VDS = 0 IG2 = 10 A, VG1S = VDS = 0 VG1S = 5 V, VG2S = VDS = 0 VG2S = 5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 3V, ID = 100 A VDS = 5 V, VG1S = 3 V, ID = 100 A VDS = 3.5 V, ID = 10 mA, VG2S = 3 V, f = 1 kHz VDS = 3.5 V, ID = 10 mA, VG2S = 3 V, f = 900 MHz
900MHz PG, NF Test Circuit
VG1 VG2 C4 C5 VD C6
R1
R2 C3 G2
R3 D L3
RFC Output (50 ) L4
Input (50 ) L1 L2
G1 S
C1
C2
C1, C2 C3 C4 to C6 R1 R2 R3 L1: 10
: : : : : :
Variable Capacitor (10 pF MAX) Disk Capacitor (1000 pF) Air Capacitor (1000 pF) 47 k 47 k 4.7 k L2:
10
26
(1 mm Copper wire) Unit : mm
8
21 L3: 29 L4: 18
3
10
7
7
RFC : 1mm Copper wire with enamel 4 turns inside dia 6 mm
Rev.1.00, May 18,2005, page 2 of 7
10
3
3SK323
Main Characteristics
Maximum Channel Power Dissipation Curve
Pch (mW)
400
(mA)
20 1.3 V
Typical Output Characteristics VG2S = 3 V 1.2 V 1.1 V
300
15 1.0 V 10 0.9 V 5 VG1S = 0.6 V 0.8 V 0.7 V 4 5 VDS (V)
Channel Power Dissipation
100
Drain Current
200
ID
0
50
100
150 Ta (C)
200
0
0
Ambient Temperature
1 2 3 Drain to Source Voltage
Note 3 : When using the glass epoxy board (50 mm x 40 mm x 1 mm )
20
(mA)
Drain Current vs. Gate1 to Source Voltage VDS =3.5 V 3.0 V
(mA)
20
Drain Current vs. Gate1 to Source Voltage VDS = 5 V 3.0 V 2.5 V 2.0 V 1.5 V
2.5 V 15 2.0 V 1.5 V 10
15
ID
Drain Current
Drain Current
ID
10
5 1.0 V VG2S = 0.5 V 0 0.0 0.5 1.0 1.5 2.0 Gate1 to Source Voltage VG1S (V)
5 1.0 V 0 0.0 0.5 1.0 Gate1 to Source Voltage VG2S = 0.5 V 1.5 VG1S 2.0 (V)
Forward Transfer Admittance vs. Gate1 to Source Voltage
Forward Transfer Admittance |yfs| (mS) Forward Transfer Admittance |yfs| (mS)
Forward Transfer Admittance vs. Gate1 to Source Voltage 50 40 30 20 2.5 V 10 1.5 V 1.0 V 0 0.0 0.5 1.0 Gate1 to Source Voltage 1.5 VG1S 2V VDS = 5 V VG2S = 3 V
50 40
VDS = 3.5 V
30
VG2S = 3 V 2.5 V
20 10 0 0.0 0.5 1.0 Gate1 to Source Voltage 1.0 V 1.5 V 1.5 VG1S
2V
2.0 (V)
2.0 (V)
Rev.1.00, May 18,2005, page 3 of 7
3SK323
Gain Reduction vs. Gate2 to Source Voltage ID = 10 mA (start) f = 900 MHz Drain Current vs. Power Gain, Noise Figure PG
40
30
3.0
Gain Reduction GR (dB)
35 30 25 20 15 10 5 0 VDS = 3.5 V 0 1 2
20
2.0
NF 10 VDS = 3.5 V VG2S = 3.0 V f = 900 MHz 0 1.0
5V
3
4 (V)
0
5
10 ID
15 (mA)
0.0 20
Gate2 to Source Voltage VG2S
Drain Current
30
Gate2 to Source Voltage vs. Power Gain, Noise Figure PG
3.0
Drain to Source Voltage vs. Power Gain, Noise Figure 30 3.0
Noise Figure NF (dB)
PG 20 2.0
20
2.0
10
NF VDS = 3.5 V ID = 10 mA (start) f = 900 MHz 1.5 2.0 2.5
1.0
NF 10 VG2S = 3.0 V ID 10 mA f = 900 MHz 1 2 3 4 VDS (V) 5 1.0
0 1.0
0.0 3.0
0
0.0
Gate2 to Source Voltage VG2S
(V)
Drain to Source Voltage
Maximum Stable Gain vs. Drain Current 30 30
Maximum Stable Gain vs. Drain Current
Maximum Stable Gain MSG (dB)
Maximum Stable Gain MSG (dB)
5V 25 20 15 10 5 0 0 VG2S = 3.0 V f = 900 MHz 15 20 ID (mA) VDS = 3.5 V
25 20 15
VG2S = 3.0 V f = 2 GHz
5V 10 5 0 0 5 10 ID 15 (mA) 20 Drain Current VDS = 3.5 V
5
10
Drain Current
Rev.1.00, May 18,2005, page 4 of 7
Noise Figure NF (dB)
Power Gain PG (dB)
Power Gain PG (dB)
Noise Figure NF (dB)
Power Gain PG (dB)
3SK323
Maximum Stable Gain vs. Frequency 40
Maximum Stable Gain MSG (dB)
30 20 10 VDS = 3.5 V VG2S = 4 V ID = 10 mA 0.5 1.0 1.5 2.0 f (GHz) 2.5 3.0
0 -10 0.0
Frequency
Rev.1.00, May 18,2005, page 5 of 7
3SK323
S parameter
(VDS = 3.5 V, VG2S = 4 V, ID = 10 mA, Zo =50 )
S11 f (GHz) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 Mag 0.996 0.989 0.973 0.956 0.940 0.920 0.899 0.879 0.858 0.840 0.816 0.794 0.772 0.752 0.734 0.727 0.754 0.825 0.877 0.890 0.882 0.867 0.851 0.834 0.816 0.795 0.771 0.744 0.713 0.677 Phase -6.0 -11.7 -17.1 -22.6 -27.8 -32.9 -37.7 -42.4 -46.9 -51.3 -55.5 -59.3 -62.8 -66.0 -68.5 -69.7 -70.0 -73.3 -80.3 -88.0 -94.7 -100.9 -106.6 -112.1 -117.5 -122.8 -128.1 -133.2 -138.1 -142.4 Mag 4.33 4.23 4.15 4.06 3.94 3.84 3.73 3.62 3.52 3.42 3.30 3.19 3.08 2.97 2.84 2.63 2.28 1.77 1.47 1.45 1.52 1.56 1.58 1.56 1.54 1.50 1.47 1.43 1.39 1.36 S21 Phase 170.1 160.5 151.2 142.1 133.5 125.0 116.7 108.6 100.5 92.5 84.4 76.2 67.8 59.2 49.4 38.2 26.6 20.3 24.7 29.7 28.9 25.0 19.9 14.4 8.8 3.2 -2.2 -7.7 -12.9 -18.3 Mag 0.002 0.003 0.003 0.004 0.004 0.003 0.004 0.005 0.010 0.014 0.020 0.028 0.036 0.048 0.058 0.069 0.079 0.092 0.111 0.136 0.162 0.192 0.223 0.256 0.294 0.333 0.374 0.416 0.458 0.497 S12 Phase 139.0 84.8 96.9 75.9 82.6 91.7 132.5 157.1 169.9 173.8 174.8 175.0 169.6 165.1 160.8 156.3 152.6 152.4 150.7 147.2 142.4 136.6 130.5 123.9 117.3 109.8 101.9 93.6 84.6 74.7 Mag 0.992 0.988 0.978 0.963 0.948 0.931 0.915 0.899 0.883 0.869 0.857 0.846 0.838 0.835 0.837 0.849 0.867 0.869 0.847 0.818 0.796 0.780 0.766 0.753 0.739 0.724 0.706 0.681 0.654 0.624 S22 Phase -6.1 -11.9 -17.7 -23.5 -28.9 -34.4 -39.6 -44.7 -49.7 -54.5 -59.3 -63.9 -68.5 -72.9 -77.3 -82.4 -88.1 -95.5 -102.1 -108.0 -112.9 -117.7 -122.4 -127.3 -132.2 -137.2 -142.2 -146.9 -151.2 -154.8
Rev.1.00, May 18,2005, page 6 of 7
3SK323
Package Dimensions
JEITA Package Code SC-61AA RENESAS Code PLSP0004ZA-A Package Name MPAK-4 / MPAK-4V MASS[Typ.] 0.013g
D e2 b1 B B e
A Q c
E
HE
Reference Symbol Dimension in Millimeters
L A A xM S A b
L1 A3 e2
LP
e
A2
A
I1
b5 yS A1 S e1
b b2 c c1 c
b1 b3 c1
I1
b4
A-A Section
B-B Section
Pattern of terminal position areas
A A1 A2 A3 b b1 b2 b3 c c1 D E e e2 HE L L1 LP x y b4 b5 e1 I1 Q
Min 1.0 0 1.0 0.35 0.55
Nom
0.1 2.7 1.35
1.1 0.25 0.42 0.62 0.4 0.6 0.13 0.11 1.5 0.95 0.85 2.8
Max 1.3 0.1 1.2 0.5 0.7
0.15 3.1 1.65
2.2 0.35 0.15 0.25
3.0 0.75 0.55 0.65 0.05 0.05 0.55 0.75 1.05
1.95 0.3
Ordering Information
Part Name 3SK324UGQuantity 3000 pcs. Taping Shipping Container
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product.
Rev.1.00, May 18,2005, page 7 of 7
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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http://www.renesas.com
(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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